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18 v, 725 a, 4 mhz cmos rrio operational amplifier data sheet ada4666 - 2 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 020 62- 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com features low power at high voltage (18 v): 725 a maximum low offset voltage : 2.2 mv maximum over entire common - mode range low input bias current: 15 pa maximum gain bandwidth product: 4 m hz typical at a v = 100 unity - gain crossov er: 4 mhz typical ?3 db closed - loop bandwidth: 2.1 mhz typical single - supply operation: 3 v to 18 v dual - supply operation: 1.5 v to 9 v unity - gain stable applications current shunt mon itors active filters portable medical equipment buffer/level shifting high impedance sensor interface s battery powered instrumentation general description the ada466 6-2 is a dual, rail - to - rail input/ output amplifier optimized for low power , high bandwidth , and wide operating supply voltage range applications. the ada466 6-2 performance is guaranteed at 3.0 v, 10 v, and 18 v power supply voltages. it is an excellent selectio n for applications that us e single- ended supplies of 3.3 v, 5 v, 1 0 v, 12 v, and 15 v, and dual supplies of 2.5 v, 3.3 v, and 5 v. the ada466 6-2 is specified over the extended industrial temperature range ( ? 40c to +125 c) and is available in 8- lead msop and 8- lead lfcsp (3 mm 3 mm) packages. pin connection diagr ams figure 1 . 8 - lead msop figure 2 . 8 - lead lfcsp figure 3 . output voltage (v oh ) to supply rail vs. load current table 1. precision low power op amps (< 1 m a) supply voltage 5 v 12 v to 16 v 30 v single ada4505-1 op196 op777 ad8500 dual ada4505 - 2 ad8657 ada4096 - 2 ad8502 op296 op727 ad8506 ada4661-2 ad8682 ad8546 ada4666-2 ad8622 quad ada4505-4 ad8659 ada4096-4 ad8504 op496 op747 ad8508 ad8684 ad8548 ad8624 out a 1 ?in a 2 +in a 3 v? 4 v+ 8 out b 7 ?in b 6 +in b 5 ada4666-2 top view (not to scale) 1 1382-001 ada4666-2 top view (not to scale) notes 1. connect the exposed p ad t o v? or le a ve it unconnected. 3 +in a 4v? 1 out a 2 ?in a 6 ?in b 5 +in b 8 v+ 7 out b 1 1366-002 1 10 100 1000 10000 0.001 0.01 0.1 1 10 100 output vo lt age (v oh ) t o supp ly rai l (mv) load current (ma) v sy = 18v ?40c +25c +85c +1 2 5c 1 1382-022
ada4666-2 data sheet rev. 0 | page 2 of 32 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? pin connection diagrams ............................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? electrical characteristics18 v operation ............................. 3 ? electrical characteristics10 v operation ............................. 5 ? electrical characteristics3.0 v operation ............................ 7 ? absolute maximum ratings ............................................................ 9 ? thermal resistance ...................................................................... 9 ? esd caution .................................................................................. 9 ? pin configurations and function descriptions ......................... 10 ? typical performance characteristics ........................................... 11 ? applications information .............................................................. 22 ? input stage ................................................................................... 22 ? gain stage .................................................................................... 23 ? output stage ................................................................................ 23 ? maximum power dissipation ................................................... 23 ? rail-to-rail input and output .................................................. 23 ? comparator operation .............................................................. 24 ? emi rejection ratio .................................................................. 25 ? current shunt monitor .............................................................. 25 ? active filters ............................................................................... 25 ? capacitive load drive ............................................................... 26 ? noise considerations with high impedance sources ........... 28 ? outline dimensions ....................................................................... 29 ? ordering guide .......................................................................... 29 ? revision history 7/13revision 0: initial version
da ta sheet ada4666 -2 rev. 0 | page 3 of 32 specifications electrical character istics 18 v operation v sy = 18 v, v cm = v sy / 2 v, t a = 25c, unless otherwise specified. table 2. parameter symbol test conditions/comments min typ max unit input characteristics offset voltage v os 0.5 2.2 mv v cm = 0 v to 18 v 2.2 mv v cm = 0 v to 18 v; ?40c t a +125c 3.5 mv offset voltage drift v os / t ?40c t a +125c 0.6 3.1 v/c input bias current i b 0.5 15 pa ?40c t a +85c 100 pa ?40c t a +125c 900 pa input offset current i os 11 pa ?40c t a +85c 30 pa ?40c t a +125c 300 pa input voltage range 0 18 v common - mode rejection ratio cmrr v cm = 0 v to 18 v 80 95 db v cm = 0 v to 18 v; ?40c t a +125c 77 db large signal voltage gain a vo r l = 100 k, v o = 0.5 v to 17.5 v 120 147 db ?40c t a +125c 120 db input resistance differential mode r indm >10 g common mode r incm >10 g input capacitance differential mode c indm 8.5 pf common mode c incm 3 pf output characteristics output voltage high v oh r l = 10 k to v cm 17.95 17.97 v ?40c t a +125c 17.94 v r l = 1 k to v cm 17.6 17.79 v ?40c t a +125c 17.58 v output voltage low v ol r l = 10 k to v cm 14 25 mv ?40c t a +125c 40 mv r l = 1 k to v cm 120 200 mv ?40c t a +125c 300 mv continuous output current i out dropout voltage = 1 v 40 ma short - circuit current i sc pulse width = 10 ms ; refer to the maximum power dissipation section 220 ma closed - loop output impedance z out f = 100 khz, a v = 1 0.2 power supply power supply rejection ratio psrr v sy = 3.0 v to 18 v 120 145 db ?40c t a +125c 120 db supply current per amplifier i sy i out = 0 ma 630 725 a ?40c t a +125c 975 a dynamic performance slew rate sr r s = 1 k , r l = 10 k, c l = 10 pf, a v = 1 2 v/s gain bandwidth product gbp v in = 10 mv p- p, r l = 10 k, c l = 10 pf, a v = 100 4 mhz unity - gain crossover ugc v in = 10 mv p - p, r l = 10 k, c l = 10 pf, a vo = 1 4 mhz ?3 db closed - loop bandwidth f ?3 db v in = 10 mv p - p, r l = 10 k, c l = 10 pf, a v = 1 2.1 mhz phase margin m v in = 10 mv p - p, r l = 10 k, c l = 10 pf, a vo = 1 60 degrees settling time to 0.1% t s v in = 1 v step, r l = 10 k, c l = 10 pf 1.3 s
ada4666 -2 data sheet rev. 0 | page 4 of 32 parameter symbol test conditions/comments min typ max unit channel separation cs v in = 17.9 v p- p, f = 10 khz, r l = 10 k 80 db emi rejection ratio of +in x emirr v in = 100 mv peak (200 mv p- p) f = 400 mhz 34 db f = 900 mhz 42 db f = 1800 mhz 50 db f = 2400 mhz 60 db noise performance total harmonic distortion plus noise thd + n a v = 1, v in = 5.4 v rms at 1 khz bandwidth = 80 khz 0.0004 % bandwidth = 500 khz 0.0008 % peak -to - peak noise e n p-p f = 0.1 hz to 10 hz 3 v p -p voltage noise density e n f = 1 khz 18 nv/hz f = 10 khz 14 nv/hz current noise density i n f = 1 khz 360 fa/hz
da ta sheet ada4666 -2 rev. 0 | page 5 of 32 electrical character istics 10 v operation v sy = 10 v, v cm = v sy / 2 v, t a = 25c, unless otherwise specified. table 3. parameter symbol test conditions/comments min typ max unit input characteristics offset voltage v os 2.2 mv v cm = 0 v to 10 v 2.2 mv v cm = 0 v to 10 v; ?40c t a +125c 3.5 mv offset voltage drift v os / t ?40c t a +125c 0.6 3.1 v/c input bias current i b 0.25 15 pa ?40c t a +85c 80 pa ?40c t a +125c 750 pa input offset current i os 11 pa ?40c t a +85c 30 pa ?40c t a +125c 270 pa input voltage range 0 10 v common - mode rejection ratio cmrr v cm = 0 v to 10 v 75 90 db v cm = 0 v to 10 v; ?40c t a +125c 72 db large signal voltage gain a vo r l = 100 k, v o = 0.5 v to 9.5 v 120 145 db ?40c t a +125c 120 db input resistance differential mode r indm >10 g common mode r incm >10 g input capacitance differential mode c indm 8.5 pf common mode c incm 3 pf output characteristics output voltage high v oh r l = 10 k to v cm 9.96 9.98 v ?40c t a +125c 9.96 v r l = 1 k to vcm 9.7 9.88 v ?40c t a +125c 9.7 v output voltage low v ol r l = 10 k to v cm 10 15 mv ?40c t a +125c 30 mv r l = 1 k to v cm 77 110 mv ?40c t a +125c 200 mv continuous output current i out dropout voltage = 1 v 40 ma short - circuit current i sc pulse width = 10 ms ; refer to the maximum power dissipation section 220 ma closed - loop output impedance z out f = 100 khz, a v = 1 0.2 power supply power supply rejection ratio psrr v sy = 3.0 v to 18 v 120 145 db ?40c t a +125c 120 db supply current per amplifier i sy i out = 0 ma 620 725 a ?40c t a +125c 975 a dynamic performance slew rate sr r s = 1 k, r l = 10 k, c l = 10 pf, a v = 1 1.8 v/s gain bandwidth product gbp v in = 10 mv p - p, r l = 10 k, c l = 10 pf, a v = 100 4 mhz unity - gain crossover ugc v in = 10 mv p - p, r l = 10 k, c l = 10 pf, a vo = 1 4 mhz ?3 db closed - loop bandwidth f ?3 db v in = 10 mv p - p, r l = 10 k, c l = 10 pf, a v = 1 2.1 mhz phase margin m v in = 10 mv p - p, r l = 10 k, c l = 10 pf, a vo = 1 60 degrees settling time to 0.1% t s v in = 1 v step, r l = 10 k, c l = 10 pf 1.3 s channel separation cs v in = 9.9 v p - p, f = 10 khz, r l = 10 k 85 db
ada4666 -2 data sheet rev. 0 | page 6 of 32 parameter symbol test conditions/comments min typ max unit emi rejection ratio of +in x emirr v in = 100 mv peak (200 mv p- p) f = 400 mhz 34 db f = 900 mhz 42 db f = 1800 mhz 50 db f = 2400 mhz 60 db noise performance total harmonic distortion plus noise thd + n a v = 1, v in =2.2 v rms at 1 khz bandwidth = 80 khz 0.0004 % bandwidth = 500 khz 0.0008 % peak -to - peak noise e n p-p f = 0.1 hz to 10 hz 3 v p -p voltage noise density e n f = 1 khz 18 nv/hz f = 10 khz 14 nv/hz current noise density i n f = 1 khz 360 fa/hz
da ta sheet ada4666 -2 rev. 0 | page 7 of 32 electrical character istics 3.0 v operation v sy = 3.0 v, v cm = v sy /2 v, t a = 25c, unless otherwise specified. table 4. parameter symbol test conditions/comments min typ max unit input characteristics offset voltage v os 0.5 2.2 mv v cm = 0 v to 3.0 v 2.2 mv v cm = 0 v to 3.0 v; ?40c t a +125c 3.5 mv offset voltage drift v os / t ?40c t a +125c 0.6 3.1 v/c input bias current i b 0.15 8 pa ?40c t a +85c 45 pa ?40c t a +125c 650 pa input offset current i os 11 pa ?40c t a +85c 30 pa ?40c t a +125c 27 pa input voltage range 0 3 v common - mode rejection ratio cmrr v cm = 0 v to 3.0 v 64 80 db v cm = 0 v to 3.0 v; ?40c t a +125c 61 db large signal voltage gain a vo r l = 100 k, v o = 0.5 v to 2.5 v 105 130 db ?40c t a +125c 105 db input resistance differential mode r indm >10 g common mode r incm >10 g input capacitance, differential mode c indm 8.5 pf common mode c incm 3 pf output characteristics output voltage high v oh r l = 10 k to v cm 2.98 2.99 v ?40c t a +125c 2.98 v r l = 1 k to v cm 2.9 2.96 v ?40c t a +125c 2.9 v output voltage low v ol r l = 10 k to v cm 4 8 mv ?40c t a +125c 15 mv r l = 1 k to v cm 25 40 mv ?40c t a +125c 65 mv continuous output current i out dropout voltage = 1 v 40 ma short - circuit current i sc pulse width = 10 ms ; refer to the maximum power dissipation section 220 ma closed - loop output impedance z out f = 100 khz, a v = 1 0.2 power supply power supply rejection ratio psrr v sy = 3.0 v to 18 v 120 145 db ?40c t a +125c 120 db supply current per amplifier i sy i o ut = 0 ma 615 725 a ?40c t a +125c 975 a dynamic performance slew rate sr r s = 1 k, r l = 10 k, c l = 10 pf, a v = 1 1.7 v/s gain bandwidth product gbp v in = 10 mv p- p, r l = 10 k, c l = 10 pf, a v = 100 4 mhz unity - gain crossover ugc v in = 10 mv p - p, r l = 10 k, c l = 10 pf, a vo = 1 4 mhz ?3 db closed - loop bandwidth f ?3 db v in = 10 mv p - p, r l = 10 k, c l = 10 pf, a v = 1 1.7 mhz settling time to 0.1% t s v in = 1 v step, r l = 10 k, c l = 10 pf 1.3 s phase margin m v in = 10 mv p- p, r l = 10 k, c l = 10 pf, a vo = 1 60 degrees channel separation cs v in = 2.9 v p - p, f = 10 khz, r l = 10 k 90 db
ada4666 -2 data sheet rev. 0 | page 8 of 32 parameter symbol test conditions/comments min typ max unit emi rejection ratio of +in x emirr v in = 100 mv peak (200 mv p- p) f = 400 mhz 34 db f = 900 mhz 42 db f = 1800 mhz 50 db f = 2400 mhz 60 db noise performance total harmonic distortion plus noise thd + n a v = 1, v in = 0.44 v rms at 1 khz bandwidth = 80 khz 0.002 % bandwidth = 500 khz 0.003 % peak -to - peak noise e n p-p f = 0.1 hz to 10 hz 3 v p -p voltage noise density e n f = 1 khz 18 nv/hz f = 10 khz 14 nv/hz current noise density i n f = 1 khz 360 fa/hz
da ta sheet ada4666 -2 rev. 0 | page 9 of 32 absolute maximum rat ings table 5. parameter rating supply voltage 20.5 v input voltage (v?) ? 300 mv to (v+) + 300 mv input current 1 10 ma differential input voltage limited by maximum input current output short - circuit duration to gnd refer to the maximum power dissipation section temperature range storage ?65 c to +150 c operating ?40 c to +125 c junction ?65 c to +150 c lead temperature (soldering, 60 sec) 300c esd 4 kv human body model 2 machine model 3 400 v field - induced charge d- device model (ficdm) 4 1.25 kv 1 the input pins have clamp diodes to the power supply pins and to each other. limit the input current to 10 ma or less when input signals exceed the power supply rail by 0.3 v. 2 applicable s tandard : mil - std - 883, method 3015.7. 3 applicable s tandard : jesd2 2- a115 - a (esd machine model standard of jedec). 4 applicable standard j esd22 - c101 c (esd ficdm standard of jedec). stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal res istance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages using a standard 4 - layer jedec board. the exposed pad of the lfcsp package is soldered to the board. table 6 . thermal resistance package type ja jc unit 8- lead msop 142 45 c/w 8- lead lfcsp 83.5 48.5 1 c/w 1 jc is measured on the top surface of the package. esd caution
ada4666 -2 data sheet rev. 0 | page 10 of 32 pin configurations and f unction descriptions figure 4 . pin configuration, 8 - lead msop figure 5 . pin configuration, 8 - lead lfcsp table 7 . pin function descriptions pin no. 1 mnemonic description 8- lead msop 8- lead lfcsp 1 1 out a output , channel a. 2 2 ?in a negative input , channel a. 3 3 +in a positive input , channel a. 4 4 v? negative supply voltage. 5 5 +in b positive input , channel b. 6 6 ?in b negative input , channel b. 7 7 out b output , channel b. 8 8 v+ positive supply voltage. n/a 9 2 e pad exposed pad. for the 8 - lead lfcsp only, connect the exposed pad to v? or leave it unconnected. 1 n/a means not applicable. 2 the exposed pad is not shown in the pin configuration diagram, figure 5 . out a 1 ?in a 2 +in a 3 v? 4 v+ 8 out b 7 ?in b 6 +in b 5 ada4666-2 top view (not to scale) 1 1382-004 ada4666-2 top view (not to scale) notes 1. connect the exposed p ad t o v? or le a ve it unconnected. 3 +in a 4v? 1 out a 2 ?in a 6 ?in b 5 +in b 8 v+ 7 out b 1 1382-005
da ta sheet ada4666 -2 rev. 0 | page 11 of 32 typical performance characteristics t a = 25 c, unless otherwise noted. figure 6. input offset voltage distribution figure 7 . input offset voltage drift distribution figure 8 . input offset voltage vs. common - mode voltage figure 9 . input offset voltage distribution figure 10 . input offset voltage drift distribution figure 11 . input offset voltage vs. common - mode voltage v os (mv) 1 1382-006 0 10 20 30 40 50 60 70 ?2.0 ?1.8 ?1.6 ?1.4 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 number of amplifiers v sy = 3v v cm = v sy /2 600 channels tcv os (v/c) 1 1382-007 0 2 4 6 8 10 12 14 16 18 20 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 number of amplifiers v sy = 3v v cm = v sy /2 C40c t a +125c 100 channels 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 v os (v) v cm (v) v sy = 3v 16 channels 1 1382-008 ?1500 ?1000 ?500 0 500 1000 1500 1 1382-009 v os (mv) 0 10 20 30 40 50 60 70 ?2.0 ?1.8 ?1.6 ?1.4 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 number of amplifiers v sy = 18v v cm = v sy /2 600 channels 1 1382-010 tcv os (v/c) 0 2 4 6 8 10 12 14 16 18 20 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 number of amplifiers v sy = 18v v cm = v sy /2 C40c t a +125c 100 channels 0 1.5 3.0 4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0 16.5 18.0 v os (v) v cm (v) v sy = 18 v 16 channels 1 1382-0 11 ?1500 ?1000 ?500 0 500 1000 1500
ada4666 -2 data sheet rev. 0 | page 12 of 32 figure 12 . input offset voltage vs. common - mode voltage figure 13 . input offset voltage vs. common - mode voltage figure 14 . small signal cmrr vs. common - mode voltage figure 15 . input offset voltage vs. common - mode voltage figure 16 . input offset voltage vs. common - mode voltage figure 17 . small signal psrr vs. common - mode voltage 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 v os (v) v cm (v) v sy = 3v 25 channels a t ?40c and +85c 1 1382-012 ?1500 ?1000 ?500 0 500 1000 1500 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 v os (v) v cm (v) v sy = 3v 25 channels a t ?40c and +125c 1 1382-013 ?1500 ?1000 ?500 0 500 1000 1500 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 1 2 3 4 5 6 7 8 9 10 small signal cmrr (db) v cm (v) v sy = 10v v cm = 400mv 1 1382-216 1.5 3.0 4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0 16.5 18.0 v os (v) v cm (v) v sy = 18v 25 channels a t ?40c and +85c 1 1382-015 ?1500 ?1000 ?500 0 500 1000 1500 0 0 1.5 3.0 4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0 16.5 18.0 v os (v) v cm (v) v sy = 18v 25 channels a t ?40c and +125c 1 1382-016 ?1500 ?1000 ?500 0 500 1000 1500 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 1 2 3 4 5 6 7 8 9 10 small signa l psrr (db) v cm (v) v sy = 10 v v sy = 400mv psr r? psr r+ 1 1382-168
da ta sheet ada4666 -2 rev. 0 | page 13 of 32 figure 18 . input bias current vs. temperature figure 19 . input bias current vs. common - mode voltage figure 20 . output voltage (v oh ) to supply rail vs. load current figure 21 . input bias current vs. temperature figure 22 . input bias current vs. common - mode voltage figure 23 . output voltage (v oh ) to supply rail vs. load current 0.1 1 10 100 1000 25 50 75 100 125 i b (pa) temperature (c) |i b +| |i b ?| v sy = 3v v cm = v sy /2 1 1382-014 ?4 ?3 ?2 ?1 0 1 2 3 0 0.5 1.0 1.5 2.0 2.5 3.0 i b (na) v cm (v) v sy = 3v v cm = v sy /2 25 c 85 c 125 c 1 1382-018 1 10 100 1000 10000 0.001 0.01 0.1 1 10 100 output vo lt age (v oh ) t o supp ly rai l (mv) load current (ma) v sy = 3v ?40c +25c +85c +1 2 5c 1 1382-019 0.1 1 10 100 1000 25 50 75 100 125 tempera ture (c) v sy = 18v i b (pa) |i b +| |i b ?| v cm = v sy /2 1 1382-017 ?4 ?3 ?2 ?1 0 1 2 3 i b (na) v cm (v) v sy = 18v v cm = v sy /2 25 c 85 c 125 c 0 2 4 6 8 10 12 14 16 18 1 1382-021 1 10 100 1000 10000 0.001 0.01 0.1 1 10 100 output vo lt age (v oh ) t o supp ly rai l (mv) load current (ma) v sy = 18v ?40c +25c +85c +1 2 5c 1 1382-022
ada4666 -2 data sheet rev. 0 | page 14 of 32 figure 24 . output voltage (v ol ) to supply rail vs. load current figure 25 . output voltage (v oh ) vs. temperature figure 26 . output voltage (v ol ) vs. temperature figure 27 . output voltage (v ol ) to supply rail vs. load current figure 28 . output voltage (v oh ) vs. temperature figure 29 . output voltage (v ol ) vs. temperature 0.1 1 10 100 10000 1000 0.001 0.01 0.1 1 10 100 output vo lt age (v ol ) t o supp ly rai l (mv) load current (ma) ?40c +25c +1 2 5c +85c v sy = 3v 1 1382-020 2.94 2.95 2.96 2.97 2.98 2.99 3.00 ?50 ?25 0 25 50 75 100 125 output vo lt age (v oh ) (v) tempera ture (c) v sy = 3v r l = 1 k? r l = 1 0k? 1 1382-024 ?50 ?25 0 25 50 75 100 125 output vo lt age (v ol ) (mv) tempera ture (c) v sy = 3v r l = 1 0k? 0 10 20 30 40 50 r l = 1 k? 1 1382-025 0.1 1 10 100 1000 10000 0.001 0.01 0.1 1 10 100 output vo lt age (v ol ) t o supp ly rai l (mv) load current (ma) v sy = 18v ?40c +25c +85c +1 2 5c 1 1382-023 ?50 ?25 0 25 50 75 100 125 output vo lt age (v oh ) (v) tempera ture (c) v sy = 18v r l = 1 k? r l = 1 0k? 17.70 17.75 17.80 17.85 17.90 17.95 18.00 1 1382-027 ?50 ?25 0 25 50 75 100 125 output vo lt age (v ol ) (mv) tempera ture (c) v sy = 18v r l = 1 0k? 0 20 40 60 80 100 120 140 160 180 200 r l = 1 k? 1 1382-028
da ta sheet ada4666 -2 rev. 0 | page 15 of 32 figure 30 . supply current vs. common - mode voltage figure 31 . supply current vs. supply voltage figure 32 . open - loop gain and phase vs. frequency figure 33 . supply current vs. common - mode voltage figure 34 . supply current vs. temperature figure 35 . open - loop gain and phase vs. frequency 0 100 200 300 400 500 600 700 800 900 1000 0 0.5 1.0 1.5 2.0 2.5 3.0 i sy per amplifier (a) v cm (v) ?40c +25c +85c +1 2 5c v sy = 3v 1 1382-026 0 200 400 600 800 1000 0 2 4 6 8 10 12 14 16 18 i sy per amplifier (a) v sy (v) ?40c +25c +85c +1 2 5c v cm = v sy /2 1 1382-030 ?90 ?45 0 45 90 135 ?20 0 20 40 60 80 10k 100k 1m 10m phase (degrees) open-loop gain (db) frequenc y (hz) c l = 0pf c l = 10pf c l = 0pf c l = 10pf v sy = 3v r l = 10k ? gain phase 1 1382-033 0 100 200 300 400 500 600 700 800 900 1000 0 3 6 9 12 15 18 i sy per amplifier (a) v cm (v) ?40c +25c +85c +1 2 5c v sy = 18v 1 1382-029 0 100 200 300 400 500 600 700 800 900 1000 ?50 ?25 0 25 50 75 100 125 i sy per amplifier (a) tempera ture (c) v sy = 3 v v sy = 10 v v sy = 18 v v cm = v sy /2 1 1382-133 10k 100k 1m 10m ?90 ?45 0 45 90 135 ?20 0 20 40 60 80 phase (degrees) open-loop gain (db) frequenc y (hz) gain phase c l = 0pf c l = 10pf c l = 0pf c l = 10pf v sy = 18v r l = 10k? 1 1382-036
ada4666 -2 data sheet rev. 0 | page 16 of 32 figure 36 . closed - loop gain vs. frequency figure 37 . output impedance vs. frequency figure 38 . cmrr vs. frequency figure 39 . closed - loop gain vs. frequency figure 40 . output impedance vs. frequency figure 41 . cmrr vs. frequency ?40 ?20 0 20 40 60 1k 10k 100k 1m 10m gain (db) frequenc y (hz) a v = 1 a v = 10 a v = 10 0 v sy = 3v c l = 5pf 1 1382-232 1k 10k 100k 100 1m 10m frequenc y (hz) 0.01 0.1 1 10 100 1k 10k v sy = 3v v cm = v sy /2 z out (?) a v = 100 a v = 10 a v = 1 1 1382-038 1k 10k 100k 100 1m 10m frequenc y (hz) 0 20 40 60 80 100 120 cmrr (db) v sy = 3v v cm = v sy /2 1 1382-039 ?40 ?20 0 20 40 60 1k 10k 100k 1m 10m gain (db) frequenc y (hz) a v = 1 a v = 10 a v = 10 0 v sy = 18v c l = 5pf 1 1382-235 1k 10k 100k 100 1m 10m frequenc y (hz) 0.01 0.1 1 10 100 1k 10k v sy = 18v v cm = v sy /2 z out (?) a v = 100 a v = 10 a v = 1 1 1382-041 1k 10k 100k 100 1m 10m frequenc y (hz) 0 20 40 60 80 100 120 cmrr (db) v sy = 18v v cm = v sy /2 1 1382-042
da ta sheet ada4666 -2 rev. 0 | page 17 of 32 figure 42 . psrr vs. frequency figure 43 . small signal overshoot vs. load capacitance figure 44 . large signal transient response figure 45 . psrr vs. frequency figure 46 . small signal overshoot vs. load capacitance figure 47 . large signal transient response 1k 10k 100k 1m 10m frequenc y (hz) 0 20 40 60 80 100 psrr (db) v sy = 3v psrr+ psrr? 1 1382-040 0 10 20 30 40 50 60 0 10 20 30 40 50 overshoot (%) ca p aci t ance (pf) v sy = 3v v in = 100mv p-p a v = 1 r l = 10k? os+ os? 1 1382-044 volt age (0.5v/div) time (5s/div) v sy = 1.5v v in = 2.5v p-p a v = 1 r l = 10k? c l = 10pf r s = 1k? 1 1382-045 1k 10k 100k 1m 10m frequenc y (hz) 0 20 40 60 80 100 psrr (db) v sy = 18v psrr+ psrr? 1 1382-043 0 10 20 30 40 50 60 0 10 20 30 40 50 overshoot (%) ca p aci t ance (pf) os+ os? v sy = 18v v in = 100mv p-p a v = 1 r l = 10k? 1 1382-047 volt age (2v/div) time (5s/div) v sy = 9v v in = 17v p-p a v = 1 r l = 10k? c l = 10pf r s = 1k? 1 1382-048
ada4666 -2 data sheet rev. 0 | page 18 of 32 figure 48 . small signal transient response figure 49 . positive overload recovery figure 50 . negative overload recovery figure 51 . small signal transient response figure 52 . positive overload recovery figure 53 . negative overload recovery volt age (20mv/div) time (2s/div) v sy = 1.5v v in = 100mv p-p a v = 1 r l = 10k? c l = 10pf 1 1382-046 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 ?1.4 ?1.2 ?1 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 output vo lt age (v) input vo lt age (v) time (2s/div) v sy = 1.5v a v = ?10 r l = 10k? c l = 10pf v in = 225mv v in v out 1 1382-050 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 output vo lt age (v) input vo lt age (v) time (2s/div) v sy = 1.5v a v = ?10 r l = 10k? c l = 10pf v in = 225mv v in v out 1 1382-051 volt age (20mv/div) time (2s/div) v sy = 9v v in = 100mv p-p a v = 1 r l = 10k? c l = 10pf 1 1382-049 ?3 0 3 6 9 12 15 18 ?6 ?5 ?4 ?3 ?2 ?1 0 1 output vo lt age (v) input vo lt age (v) time (2s/div) v sy = 9v a v = ?10 r l = 10k? c l = 10pf v in = 1.35v v in v out 1 1382-053 ?12 ?9 ?6 ?3 0 3 6 9 ?5 ?4 ?3 ?2 ?1 0 1 2 output vo lt age (v) input vo lt age (v) time (2s/div) v sy = 9v a v = ?10 r l = 10k? c l = 10pf v in = 1.35v v in v out 1 1382-054
da ta sheet ada4666 -2 rev. 0 | page 19 of 32 figure 54 . positive settling time to 0.1% figure 55 . negative settling time to 0.1% figure 56 . voltage noise density vs. frequency figure 57 . positive settling time to 0.1% figure 58 . negative settling time to 0.1% figure 59 . voltage noise density vs. frequency volt age (500mv/div) volt age (1mv/div) time (400ns/div) v sy = 1.5v v in = 1v p-p r l = 10k? c l = 10pf a v = ?1 error band output input 1 1382-052 volt age (500mv/div) time (400ns/div) v sy = 1.5v v in = 1v p-p r l = 10k? c l = 10pf a v = ?1 error band output input volt age (1mv/div) 1 1382-056 1 10 100 1k volt age noise densit y (nv/hz) 1k 10k 100k 10 100 1m 10m frequenc y (hz) v sy = 3v v cm = v sy /2 a v = 1 1 1382-057 volt age (500mv/div) time (400ns/div) v sy = 9v v in = 1v p-p r l = 10k? c l = 10pf a v = ?1 error band output input volt age (1mv/div) 1 1382-055 volt age (500mv/div) time (400ns/div) v sy = 9v v in = 1v p-p r l = 10k? c l = 10pf a v = ?1 error band output input volt age (1mv/div) 1 1382-059 1 10 100 1k volt age noise densit y (nv/hz) 1k 10k 100k 10 100 1m 10m frequenc y (hz) v sy = 18v v cm = v sy /2 a v = 1 1 1382-060
ada4666 -2 data sheet rev. 0 | page 20 of 32 figure 60 . 0.1 hz to 10 hz noise figure 61 . output swing vs. frequency figure 62 . thd + n vs. frequency figure 63 . 0.1 hz to 10 hz noise figure 64 . output swing vs. frequency figure 65 . thd + n vs. frequency volt age (1v/div) time (2s/div) v sy = 3v v cm = v sy /2 a v = 1 1 1382-058 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 10 100 1k 10k 100k 1m output swing (v) v sy = 3v v in = 2.9v r l = 10k? c l = 10pf a v = 1 frequenc y (hz) 1 1382-062 0.001 0.01 0.1 1 10 100 1k 10k 100k thd + n (%) frequenc y (hz) 80khz lo w-p ass fi lter 500khz lo w-p ass fi lter v sy = 3v a v = 1 r l = 10k? v in = 440mv rms 1 1382-063 volt age (1v/div) time (2s/div) v sy = 18v v cm = v sy /2 a v = 1 1 1382-061 0 2 4 6 8 10 12 14 16 18 20 10 100 1k 10k 100k 1m output swing (v) v sy = 18v v in = 17.9v r l = 10k? c l = 10pf a v = 1 frequenc y (hz) 1 1382-065 0.0001 0.001 0.01 0.1 1 thd + n (%) 10 100 1k 10k 100k frequenc y (hz) 80khz lo w-p ass fi lter 500khz lo w-p ass fi lter v sy = 18v a v = 1 r l = 10k? v in = 5.4v rms 1 1382-066
da ta sheet ada4666 -2 rev. 0 | page 21 of 32 figure 66 . thd + n vs. amplitude figure 67 . channel separation vs. frequency figure 68 . thd + n vs. amplitude figure 69 . channel separation vs. frequency 0.001 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 thd + n (%) amplitude (v rms) 80khz lo w-p ass fi lter 500khz lo w-p ass fi lter v sy = 3v a v = 1 r l = 10k? f = 1khz 1 1382-064 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 100 1k 10k 100k channe l se p ar a tion (db) frequenc y (hz) v in = 0.5v p-p v in = 1.5v p-p v in = 2.9v p-p v sy = 3v a v = 100 r l = 10k? 500khz lo w-p ass fi lter 1 1382-068 0.0001 0.001 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 thd + n (%) amplitude (v rms) v sy = 18v a v = 1 r l = 10k? f = 1khz 80khz lo w-p ass fi lter 500khz lo w-p ass fi lter 1 1382-067 10 100 1k 10k 100k channe l se p ar a tion (db) frequenc y (hz) ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 v in = 0.5v p-p v in = 9v p-p v in = 17.9v p-p v sy = 18v a v = 100 r l = 10k? 500khz lo w-p ass fi lter 1 1382-069
ada4666 -2 data sheet rev. 0 | page 22 of 32 applications informa tion figure 70 . simplified schematic the ada466 6-2 is a low power, ra il - to - rail input and output , cmos amplifier that operates over a wide supply voltage range of 3 v to 18 v. to achieve a rail - to - rail input and output range with very low supply current, the ada466 6-2 uses unique input and output stages. input stage figure 70 shows the simplified schematic of the ada466 6-2 . the amplifier uses a three - stage architecture with a fully differential input stage to achieve excellent dc performance specifications. the input stage comprises two differential transistor pairs a nmos pair (m1, m2), a pmos pair (m3, m4) and folded - cascode transistors (m5 to m12). the input common - mode voltage determines which differential pair is active. the pmos differential pair is active for most of the input common - mode range. the nmos pair is required for input vol tages up to and including the upper supply rail. this topology allows the amplifier to maintain a wide dynamic input voltage range and maximize signal swing to both supply rails. the proprietary high voltage protection circuitry in the ada466 6-2 minimizes the common - mode voltage changes seen by the amplifier input sta ge for most of the input common - mode range. this results in the amplifier hav ing excellent disturbance rejection when operating in this preferred common - mode range. the performance benefits of operating within this preferred ra nge are shown in the psrr vs. v cm ( see figure 17), cmrr vs. v cm ( see figure 14 ) and v os vs. v cm graphs ( see figure 8 , figure 11, figure 12, figure 13, figure 15, and figure 16). the cmrr performance benefits of the reduced common - mode range are guaranteed at final test a nd shown in the electrical characteristics (see tabl e 2 to table 4 ). for most of the input common - mode voltage range, the pmos differential pair is active. when the input common - mode voltage is within a few v olts of the power supplies, the input transistors are exposed to these voltage changes. as the common - mode voltage approaches the positive power supply, the active differential pair changes from the pmos pair to the nmos pair. differen tial pairs commonly exhibit different offset voltages. the handoff of control from one differential pair to the other creates a step like characteristic that is visible in the v os vs. v cm graph s (see figure 8 , figure 11, figure 12 , figure 13 , figure 15 , and figure 16) . this characteristic is inherent in all rail - to - rail input amplifiers that use the dual differential pair topology . additional steps in the v os vs. v cm graphs are visible as the common - mode voltage approaches the negative power supply. these changes are a result of the load transistors (m5, m6) running out of headroom. as the load transistors are forced into the triode region of operation, the mismatch of their drain impedance bec omes a significant portion of the amplifier offset. this effect can also be seen in the v os vs. v cm graphs ( see figure 8 , f igure 11, figure 12, figure 13, figure 15 , and figure 16). current source i2 drives the pmos transistor pair. as the input common - mode voltage approache s the upper power supply , this current is reduced to zero. at the same time , a replica current source , i1, is increased from zero to enable the nmos transistor pair. the ada466 6-2 achieves its high performance specifications by using low voltage mos devices for its differential inputs. these low voltage mos devices offer excellent noise and bandwidth per unit of current. the input stage is isolated from the high system voltages with proprietary protection circuitry. this regu - lation circuitry protects the input devices from the high supply voltages at which the amplifier can operate. v+ v? +in x out x r1 d1 m1 m2 m3 m11 m12 c1 c3 c2 v1 m9 m10 m7 m8 q1 q2 m5 high vo lt age protection m6 m15 m21 m22 m16 m13 m14 m19 m20 m17 m18 m4 d2 r2 i1 i3 i2 ?in x high vo lt age protection 1 1382-169
da ta sheet ada4666 -2 rev. 0 | page 23 of 32 the input devices are also protected from large differential input voltages by clamp diodes (d1 and d2). these diodes are buffered from the inputs with two 120 ? resistors (r1 and r2). the diodes conduct significant current whenever the differential voltage exceeds approx imately 600 mv; in this condition, the differential input resistance falls to 240 ? . it is possible for a significant amount of current to flow through these protection diodes. the user must ensure that current flowing into the input pins is limited to the absolute maximum of 10 ma. g ain stage the second sta ge of the amplifier is compose d of an npn differential pair (q1,q2) and folded cascode tran sistors (m13 to m20). the amplifier features nested miller compensation (c1 to c3). output stage the ada466 6-2 features a complementary output stage consist ing of the m21 and m22 transistors. these transistors are configured in a class ab topology and are biased by the voltage source, v1. this topology allows the output voltage to go within millivolts of the suppl y rails, achieving a rail - to - rail output swing. the output voltage is limited by the output impedance of the transis tors, which are low r on mos devices. the output voltage swing is a function of the load current and can be estimated using the o utput v olta ge to the s upply r ail vs. l oad c urrent graphs ( see figure 20 , figure 23 , figure 24 , and figure 27 ). the high voltage and high current capability of the ada466 6-2 output stage requires the user to ensure that it operates wit hin the thermal safe operating area (see the maximum power dissipation section ). maximum power dissip ation the ada466 6-2 is capable of driving an output current up to 220 ma. however, the usable output load current drive is limited to the maximum power dissipation allowed by the device package. the absolute maximum junction temperature fo r the ada466 6-2 is 150 c (see table 5 ). the junction temperature can be estimated as follow s: t j = p d ja + t a the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated by t he output stage transistor. it can be calculated as follows: p d = (v sy i sy ) + ( v sy ? v out ) i load where: v sy is the power supply rail . i sy is the quiescent current . v out is the output of the amplifier . i load is the output load . do not exceed the maximum junction temperature for the device , 150 c. exceeding the junction temperature limit can cause degradation in the parametric performance or even destroy the device. to ensure proper operation, it is necessary to observe the maximum power derating curves. figure 71 shows the maximum safe power dissipation in the package vs. the ambi ent temperature on a standard 4 - layer jedec board . the exposed pad of the lfcsp package is soldered to the board. figure 71 . maximum power dissipation vs. ambient temperature refer to technical article ms - 2251, data sheet intricacies absolute maximum ratings and thermal resistances , for more information. rail - to -rail input and output the ada466 6-2 feature s rail - to - rail input and output with a supply voltage from 3 v to 18 v. figure 72 shows the input and output waveforms of the ada466 6-2 configured as a unity - gain buffer with a supply voltage of 9 v . with an input voltage of 9 v, t h e ada466 6-2 allow s the output to swing very close to both rails. additionally, it do es not exhibit phase reversal. figure 72 . rail - to - rail input and output 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 25 50 75 100 125 150 maximum power dissi pa tion (w) ambient temper a ture (c) 8- lead lf csp ja = 83 .5 c /w 8- lead msop ja = 14 2 c /w t j max = 150 c 1 1382-371 volt age (v) time (200s/div) ?10 ?8 ?6 ?4 ?2 0 2 4 8 6 10 v in v out v sy = 9v v in = 9v a v = 1 r l = 10k? c l = 10pf 1 1382-072
ada4666 -2 data sheet rev. 0 | page 24 of 32 comparat or operation an op amp is designed to operate in a closed - loop configuration with feedback from its output to its inverting input. figure 73 shows the ada466 6-2 c onfigured as a voltage follower with an input voltage that is always kept at the midpoint of the power supplies. the same configuration is applied to the unused channel. a1 an d a2 indicate the placement of ammeters to measure supply current. i sy + refers to the current flowing from the upper supply rail to the op a mp, and i sy ? refers to the current flowing from the op amp t o the lower supply rail. as shown in figure 74 , in normal operating condition s , the total current flowing into the op amp is equivalent to the total current f lowing out of the op amp, where i sy + = i sy ? = 630 a per amplifier at v sy = 18 v. figure 73 . voltage follower figure 74 . supply current vs. supply voltage (voltage follower) in contrast to op amps, comparato rs are designed to work in an open - loop configuration and to drive logic circuits. although op a mps are different from comparators, occasionally an unused section of a d ual op amp is used as a comparator to save board space and cost ; however, this is not recommended for the ada466 6-2 . figure 75 and figure 76 show the ada466 6-2 configured as a com parator, with 100 k ? resistors in series with the input pins. any unused channels are configured as buffers with the input voltage kept at the midpoint of the power supplies. figure 75 . comparator a figure 76 . comparator b figure 77 shows the supply currents for both comparator c onfigurations. in compara tor mode, t he ada466 6-2 does not power up completely. for more information about configuring using op amps as comparators, see the an - 849 application note , using op amps as comparators . figure 77 . supply current vs. supply voltage ( ada466 6-2 as a comparator) ada4666-2 1/2 a1 100k? 100k? i sy + +v sy v out ?v sy i sy ? a2 1 1382-266 0 100 200 300 400 500 600 700 0 2 4 6 8 10 12 14 16 18 i sy per amplifier (a) v sy (v) 1 1382-071 a1 100k? 100k? i sy + +v sy v out ?v sy i sy ? a2 ada4666-2 1/2 1 1382-268 a1 100k? 100k? i sy + +v sy v out ?v sy i sy ? a2 ada4666-2 1/2 1 1382-269 0 100 200 300 400 500 600 700 0 2 4 6 8 10 12 14 16 18 i sy per amplifier v sy (v) com p ar at or a com p ar at or b 1 1382-074
data sheet ada4666-2 rev. 0 | page 25 of 32 emi rejection ratio circuit performance is often adversely affected by high frequency electromagnetic interference (emi). when the signal strength is low and transmission lines are long, an op amp must accurately amplify the input signals. however, all op amp pinsthe noninverting input, inverting input, positive supply, negative supply, and output pinsare susceptible to emi signals. these high frequency signals are coupled into an op amp by various means, such as conduction, near field radiation, or far field radiation. for instance, wires and pcb traces can act as antennas and pick up high frequency emi signals. amplifiers do not amplify emi or rf signals due to their relatively low bandwidth. however, due to the nonlinearities of the input devices, op amps can rectify these out-of-band signals. when these high frequency signals are rectified, they appear as a dc offset at the output. to describe the ability of the ada4666-2 to perform as intended in the presence of electromagnetic energy, the electromagnetic interference rejection ratio (emirr) of the noninverting pin is specified in table 2, table 3, and table 4 of the specifications section. a mathematical method of measuring emirr is defined as follows: emirr = 20 log ( v in_peak /v os ) figure 78. emirr vs. frequency current shunt monitor many applications require the sensing of signals near the positive or negative rail. current shunt monitors are one such application and are mostly used for feedback control systems. they are also used in a variety of other applications, including power metering, battery fuel gauging, and feedback controls in electrical power steering. in such applications, it is desirable to use a shunt with very low resistance to minimize the series voltage drop. this not only minimizes wasted power but also allows the measurement of high currents while saving power. the low input bias current, low offset voltage, and rail-to-rail feature of the ada4666-2 makes the amplifier an excellent choice for precision current monitoring. figure 79 shows a low-side current sensing circuit, and figure 80 shows a high-side current sensing circuit. current flowing through the shunt resistor creates a voltage drop. the ada4666-2 , configured as a difference amplifier, amplifies the voltage drop by a factor of r2/r1. note that for true difference amplification, matching of the resistor ratio is very important, where r2/r1 = r4/r3. the rail-to-rail output feature of the ada4666-2 allows the output of the op amp to almost reach its positive supply. this allows the current shunt monitor to sense up to approximately v sy /(r2/r1 r s ) amperes of current. for example, with v sy = 18 v, r2/r1 = 100, and r s = 100 m, this current is approxi- mately 1.8 a. figure 79. low-side current sensing circuit figure 80. high-side current sensing circuit active filters active filters are used to separate signals, passing those of interest and attenuating signals at unwanted frequencies. for example, low-pass filters are often used as antialiasing filters in data acquisition systems or as noise filters to limit high frequency noise. the high input impedance, high bandwidth, low input bias current, and dc precision of the ada4666-2 make it a good fit for active filters application. figure 81 shows the ada4666-2 in a four-pole sallen-key butterworth low-pass filter configuration. the four-pole low-pass filter has two complex conjugate pole pairs and is implemented by cascading two two-pole low-pass filters. section a and section b are configured as two-pole low- pass filters in unity gain. table 8 shows the q requirement and pole position associated with each stage of the butterworth filter. refer to chapter 8, analog filters , in linear circuit design handbook , available at www.analog.com/analogdialogue , for pole locations on the s plane and q requirements for filters of a different order. 20 40 60 80 100 120 140 10m 100m 1g 10g emirr (db) frequency (hz) v sy = 3v to 18v v in = 100mv peak v in = 50mv peak 11382-075 supply r l r s r1 r2 r4 r3 v sy i i v out * 1/2 ada4666-2 *v out = amplifier gain voltage across r s = r2/r1 r s i 11382-079 1/2 ada4666-2 supply r l r s r3 r4 r2 r1 v sy i i v out * *v out = amplifier gain voltage across r s = r2/r1 r s i 11382-080
ada4666 -2 data sheet rev. 0 | page 26 of 32 figure 81 . four - pole low - pass filter table 8. q requirements and pole position s section poles q a ?0.9239 j0.3827 0.5412 b ?0.3827 j0.9239 1.3065 the sallen - key topology is widely used due to its simple design with few circuit elements. this topology provides the user the flexibility of implementing either a low - pass or a high - pass filter by simply interchanging th e resistors and capacitors. the ada466 6-2 is configured in unity gain with a corner frequency at 10 k hz. an active filter requires an op amp with a unity - gain bandwidth that is at least 100 times greater than the product of the corner frequency, f c , and the quality factor, q. the resistors and capacit ors are also important in deter mining the perfor- m ance over manufacturing tolerances, time , and temperature. at least 1% or better tolerance resistors and 5% or better tolerance capacitors are recommended. fi gure 82 shows the frequency response of the low - pass sallen - key filter , where : v out 1 is the output of the first stage . v out 2 is the output of the second stage . v out 1 shows a 40 db/decade roll - off and v out 2 shows a n 80 db/decade roll - off. t he transition band becomes sharper as the order of the filter increases. figure 82 . low - pass filter: gain vs. frequency c apacitive l oad d rive the ada466 6-2 can safely drive capacitive loads of up to 50 pf in any configuration. as with most amplifiers, driving larger capacitive loads than specified may cause excessive overshoot and ringing, or even osc illation. heavy capacitive load reduces phase margin and causes the amplifier frequency response to peak. peaking corresponds to overshooting or ringing in the time domain. therefore, it is recommended that external compensa tion be used if the ada466 6-2 must drive a load exceeding 50 pf. this compensation is particularly important in the unity - gain configuration , which is the worst case for stability. a quick and easy way to stabilize the op amp for capacitive load drive is by adding a series resistor, r iso , between the amplifier output terminal and the load capacitance, as shown in figure 83. r iso isolates the amplifier output and feedback network from the capacitive load. however, with this compensation scheme, the output impedance as seen by the load increases , and this reduces gain accuracy. figure 83 . stability compensation with isolating resistor , r iso figure 84 shows the effect of the compensation scheme on the frequency response of the amplifier in unity - gain configuration driving 250 pf of load . 1/2 ?v sy v in +v sy v out1 c1 5.6nf ada 4666 -2 se ct io n b se ct io n a r2 2. 55k ? r1 2. 55k ? c2 6.8nf 1/2 ?v sy +v sy v out2 c3 1nf ada4666-2 r4 6. 19k ? r3 6. 19k ? c4 6.8nf 1 1382 - 081 ?120 ?100 ?80 ?60 ?40 ?20 0 20 100 1k 10k 100k 1m gain (db) v sy = 9v v out 1 v out 2 v in = 50mv p-p frequenc y (hz) 1 1382-082 1/2 ?v sy v in +v sy v out c l ada4666-2 r iso 1 1382-083
da ta sheet ada4666 -2 rev. 0 | page 27 of 32 figure 84 . frequency resp onse of compensation scheme figure 85 shows t he output response of the unity - gain amplifier driving 250 pf of capacitive load. with no compensation, the a mplifier is unstable. figure 86 to figure 88 show the amplifier output response with 210 ?, 301 ? , and 750 ? of r iso compensation. note that with lower r iso values, ringing is still noticeable , whereas with higher r iso values, higher frequency signal s are filtered out. figure 85 . output response with no compensation (r iso = 0 ?) figure 86 . output response (r iso = 210 ?) figure 87 . output response (r iso = 301 ?) figure 88 . output response (r iso = 750 ?) 10k 100k 1m 10m closed-loo p gain (db) r iso = 0? r iso = 210? r iso = 301? r iso = 499? frequenc y (hz) 10 0 ?10 ?20 ?30 ?40 ?50 1 1382-084 volt age (50mv/div) time (10s/div) v sy = 9v v in = 100mv p-p a v = 1 c l = 250pf r iso = 0? 1 1382-085 volt age (20mv/div) time (10s/div) v sy = 9v v in = 100mv p-p a v = 1 c l = 250pf r iso = 210? 1 1382-086 volt age (20mv/div) time (10s/div) v sy = 9v v in = 100mv p-p a v = 1 c l = 250pf r iso = 301? 1 1382-087 volt age (20mv/div) time (10s/div) v sy = 9v v in = 100mv p-p a v = 1 c l = 250pf r iso = 750? 1 1382-088
ada4666 -2 data sheet rev. 0 | page 28 of 32 noise considerations with high impedance sources current noise from input terminals can become a dominant contributor to the total circuit noise when an amplifier is driven with a high impedance source. unlike bipolar amplifiers, cmos amplifiers like the ada466 6-2 do not have an intrinsic shot noise source at the input terminals. the small amount of shot noise present is produced by the reverse saturation current in the esd protection diodes. this current noise is typically on the order of 1 fa/hz to 10 fa/hz . therefore, to measure current noise in this r ange, a large source impedance of greater than 10 g is required. for the ada466 6-2 , the more relevant discussion centers around an effect referred to as blowback noise. the blowback effect comes from noise in the tail current source of the amplifier , which is capacitively coupled to the amplifier inputs through the gate - to - source capacitance (c gs ) of the input transistors. this blowback noise is multiplied by the so urce impedance and appears as voltage noise at the input terminal. a 10 increase in the source impedance results in a 10 increase in the voltage noise due to blowback. the blo wback noise spectrum has a high - pass response at low frequencies due to c gs coupling. at high frequencie s, the spectrum tends to roll off with two poles: an internal pole due to parasitic capacitances of the tail current source and an external pole due to parasitic capacitances on the pcb. figure 89 shows the voltage noise density of the ada466 6-2 with source impedances of 1 m and 10 m . at low frequencies (< 1 hz to 10 hz), the amplifier 1/f voltage noise dominates the spectrum. at moderate frequencies, the spectrum flattens due to the thermal noise of the source resistors. as the frequency increases, blowback noise dominates and causes the voltage noise spect rum to increase. the noise spectrum continues to increase until it reaches either the internal or external pole frequency. after these poles, the spectrum starts to decrease. figure 89 . voltage noise density vs. frequency (with i nput series resistor , r s ) figure 90 . current noise density vs. frequency figure 90 shows the current noise density of the ada466 6-2 with source impedances of 1 m and 10 m . this current noise is extracted on ly from the voltage noise density curves in the frequency band where blowback noise is the dominant contributor. at low frequencies , the noise measurement is dominated by resistor thermal noise and amplifier 1/f noise. at high frequencies, parasitic capaci tances dominate the source impedance. the uncertainty of this scale factor prevents an accurate current noise measurement for the entire frequency range. blowback noise is present in all amplifiers. the magnitude of the effect depends on the size of the in put transistors and the construction of the biasing circuitry. cmos amplifiers typically have more blowback noise than jfet amplifiers due to noisier mos transistor biasing. on the other hand, bipolar amplifiers typically do not exhibit blowback noise beca use the large base current shot noise masks any blowback noise present. 0.1 1 10 0.01 0.1 1 10 100 1k 10k 100k volt age noise densit y (v/hz) frequenc y (hz) r s = 10 m? r s = 1 m? 1 1382-300 0.01 0.1 1 0.01 0.1 1 10 100 1k 10k 100k curr ent no ise density (pa/ h z) frequenc y (hz) r s = 1 m? r s = 1 0m? noise measurement limitation noise bandwidth limitation 1 1382-301
da ta sheet ada4666 -2 rev. 0 | page 29 of 32 outline dimensions figure 91 . 8 - lead mini small outline package [msop] (rm - 8) dimensions sho wn in millimeters figure 92 . 8 - lead lead frame chip scale package [lfcsp_wd] 3 mm 3 mm body, ve ry very thin, dual lead (cp -8- 11 ) dimensions shown in millimeters ordering guide model 1 temperature range package description package option branding ada4666-2acpz- r7 ?40c to +125c 8- lead lfcsp_wd cp-8-11 a34 ada4666-2acpz- rl ?40c to +125c 8- lead lfcsp_wd cp-8-11 a34 ada4666- 2armz ?40c to +125c 8- lead msop rm -8 a34 ada4666- 2armz -rl ?40c to +125c 8- lead msop rm -8 a34 ada4666- 2armz -r7 ?40c to +125c 8- lead msop rm -8 a34 1 z = rohs compliant part. compliant to jedec standards mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b 2.44 2.34 2.24 top view 8 1 5 4 0.30 0.25 0.20 bottom view pin 1 index are a sea ting plane 0.80 0.75 0.70 1.70 1.60 1.50 0.203 ref 0.05 max 0.02 nom 0.50 bsc exposed pa d 3.10 3.00 sq 2.90 pin 1 indic at or (r 0.15) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08 0.50 0.40 0.30 compliant to jedec standards mo-229-weed 1 1-28-2012-c 0.20 min
ada4666 -2 data sheet rev. 0 | page 30 of 32 notes
da ta sheet ada4666 -2 rev. 0 | page 31 of 32 notes
ada4666 -2 data sheet rev. 0 | page 32 of 32 notes ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11382 -0- 7/13(0)

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